Recently, copper wirings (interconnects) have come to be used as metal wirings in semiconductor devices for decreasing the electrical resistance. However, if copper wirings are used, electromigration or stress migration of copper wirings at the bottom of via-holes, adapted for forming vias to be connected to the copper wirings, is becoming of a problem. Patent Document 1 discloses a technique comprising forming copper silicide on the top of a copper wiring formed by a copper-containing metal followed by forming a via thereon. This improves resistance against migration of the copper wiring.
Patent Document 2 discloses a technique comprising exposing a layered structure, composed of a Cu film sandwiched between barrier films, to a silane gas, and selectively forming a copper silicide layer only on a portion of the wiring where copper has been exposed.
[Patent Document 1]
Japanese Patent Kokai Publication No. JP-P2004-96052A
[Patent Document 2]
Japanese Patent Kokai Publication No. JP-A-9-321045